1. Field of the Invention
The present invention relates to a semiconductor memory device of a type designed to reduce noises resulting from a capacitance coupling between the neighboring bit lines.
2. Description of the Prior Art
Examples of prior art semiconductor memory devices are shown in FIGS. 12 and 13, respectively. The prior art semiconductor memory device shown in FIG. 12 is generally referred to as an open bit-line architecture and comprises a plurality of sense amplifiers (only three of which are shown by 131, 132 and 133) of differential type arranged in one direction, bit lines B and B extending outwardly from opposite sides of each sense amplifier 131, 132 and 133, a plurality of word lines W and a dummy word line DW both intersecting the bit lines B, and a plurality of word lines W and a dummy word line DW intersecting the bit lines B. At the intersection between each bit line B or B and each word line W, a memory cell M (as indicated by the single circle) is disposed and connected with the respective bit line B or B and the respective word line W and, similarly, at the intersection between each bit line B or B and each dummy word line DW, a dummy cell D (as indicated by the double circle) is disposed and connected with the respective bit line B or B and the respective dummy word line DW.
The prior art semiconductor memory device shown in FIG. 13 is generally referred to as a folded bit-line architecture and comprises a plurality of sense amplifiers (only three of which are shown by 141, 142 and 143), a pair of bit lines B and B extending outwardly from one side of each sense amplifier 141, 142 and 143, a plurality of word lines W and a dummy word line DW intersecting the bit lines B and B of each pair. At the intersection between each word line W and each of the bit lines B and B of each pair, a memory cell M is disposed and connected with the respective word line W and the respective bit line B or B and, similarly, at the intersection between each bit line B or B and the dummy word line DW, a dummy cell is disposed and connected with the respective bit line B or B and the dummy word line DW. So that the memory cell M and the dummy cell D connected with the bit lines B and B of each pair will not be selected simultaneously by the single word line W, the memory cells and the dummy cells on the bit lines B and B of all pairs are so disposed as to intersect alternating members of the word lines W.
The semiconductor memory device of open bit-line architecture shown in FIG. 12 operates in the following manner. At the outset, when one of the word lines W is selected according to an input address signal, the dummy cells D connected with one of the dummy word lines DW which is positioned on one side of each sense amplifier 131, 132 and 133 opposite to the side adjacent said one of the word lines W are charged to a reference potential (which is normally a voltage intermediate between "H" and "L"). Then, after the paired bit lines B and B have been charged (precharged) to the same potential, said word line W and said dummy word line DW are activated to conduct the memory cells M and the dummy cells D, connected respectively therewith, to said paired bit lines B and B. Once this occurs, potential differences are created between the paired bit lines B and B by the action of the charge stored on the memory cells and the dummy cells D, which difference is differentially amplified by the associated sense amplifiers 131, 132 and 133, wherefore one of the paired bit lines which is held at a higher potential is equalized to the potential of an electric power source while the other of the paired bit lines which is held at a lower potential is equalized to a zero potential. Where the semiconductor memory device operates in this way, the potential at the bit line B or the bit line B fluctuates according to the contents of data stored in the memory cells M then brought into a conductive state and, therefore, the case would occur in which the potential at the neighboring bit line B or the neighboring bit line B varies in an opposite phase. In such case, the potential difference between the paired bit lines B and B will be reduced by the effect of an interference noise resulting from a capacitance coupling between the neighboring bit lines B or the neighboring bit lines B, causing the sense amplifiers 131, 132 and 133 to operate erroneously or resulting in a reduction in the data reading speed.
On the other hand, in the prior art semiconductor memory device of folded bit-line architecture shown in FIG. 13, it may occur that a potential variation occurring in the bit lines B and B extending respectively from the sense amplifier 142 and the sense amplifier 141, which are neighboring with each other, and a potential variation occurring in the bit lines B and B extending respectively from the sense amplifier 142 and the sense amplifier 143 which are neighboring with each other, will be opposite in phase to each other. Once this occur, the sense amplifier 142 will operate erroneously, or it may constitute a cause of reduction in a reading speed. In addition, in the case of this folded bit-line architecture, since during the operation respective potential variations occurring on the bit lines B and B of a pair associated with, for example, the sense amplifier 142 will become opposite in phase to each other, this may cause the sense amplifier to operate erroneously or it may constitute a cause of reduction in reading speed.
In view of the problem inherent in the folded bit-line architecture, a sophisticated version thereof has been develpped, which is known as a twisted bit-line architecture. The prior art semiconductor memory device of twisted bit-line architecture is shown in FIG. 14, wherein each pair of bit lines B and B extending outwardly from each of a plurality of sense amplifiers (only three of which are shown by 151, 152 and 153) are twisted. According to the twisted bit-line architecture, one pair of the bit lines B and B and another pair of the bit lines B and B are averagely spaced an equal distance from each other and, therefore, an interference nose resulting from the bit lines B or the bit lines B extending from, for example, the neighboring sense amplifiers 151 and 153 will match in phase with and be equal in magnitude to the paired bit lines B and B extending from the sense amplifier 152. Because of this, although the influence of the neighboring bit lines B and B will be small as compared with that in the folded bit-line architecture, the interference noise between the paired bit lines B and B associated with the same sense amplifier 152 will not be removed and, therefore, the sense amplifier tends to operate erroneously, accompanied by a reduction in reading speed.